Existing field programmable gate array (FPGA) integrated circuits typically have programmable input/output circuitry that includes dedicated drivers for different input/output standards. FIG. 1 illustrates an example of a prior art input/output (IO) circuit in an FPGA integrated circuit (IC) that includes five dedicated driver circuits 101-104 and 109 coupled to pads 105-106 of the IC. The IO circuit of Figure (FIG.) 1 includes two single-ended (SE) double data rate (DDR) transmitter (TX) driver circuits 101 and 103, a low voltage differential signaling (LVDS) transmitter driver circuit 102, a data strobe (DQS) DDR receiver (RX) driver circuit 104, and an LVDS receiver driver circuit 109.
FIG. 2 illustrates further details of the three prior art transmitter driver circuits 101-103 of FIG. 1. FIG. 2 shows p-channel field-effect transistors (PFETs) 201-204, n-channel field-effect transistors (NFETs) 211-216, pads 105-106 of the IC, current sources 231-232, feedback amplifier circuit 235, resistors 241-242, and switch circuits 251-252.
The DDR TX driver circuit 101 includes transistors 201 and 211, and the DDR TX driver circuit 103 includes transistors 204 and 216. When the switch circuits 251-252 are open (i.e., non-conductive), DDR TX driver circuits 101 and 103 function as single-ended voltage mode driver circuits that drive two single-ended signals PDRVP/NDRVP and PDRVN/NDRVN to pads 105 and 106, respectively. Although only one PFET and only one NFET are shown in each of driver circuits 101 and 103 in FIG. 2, each of the driver circuits 101 and 103 has multiple PFETs in parallel and multiple NFETs in parallel that may drive an output signal to the respective pad 105 or 106.
The LVDS TX driver circuit 102 includes PFETs 202-203, NFETs 212-215, current sources 231-232, resistors 241-242, and amplifier circuit 235. When the switch circuits 251-252 are closed (i.e., conductive), the LVDS TX driver circuit 102 functions as a differential current mode driver circuit. Feedback amplifier circuit 235 controls the currents through current sources 231-232 based on the voltage difference between the common mode voltage VCM between switch circuits 251-252 and a constant voltage of 1.25 volts. Driver circuit 102 drives the differential signal PDRVP/NDRVP minus PDRVN/NDRVN to pads 105 and 106. The LVDS and DDR driver circuits 101-103 have separate programmable current and drive strength for different platform requirements.